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orderin g numbe r : ena1677 bi-cmos ic for variable speed control three-phase brushless motor predriver LV8104V overview the LV8104V is a pre-driver ic designed for variable speed control of 3-phase brushless motors. it can be used to implement both upper and low output n-channel power fet drive circuit using a built-in charge pump circuit. high-efficiency drive is possible through the use of direct pwm drive and synchronous rectifyication. functions ? v cc max = vg max = 42v ? three-phase bipolar direct pwm drive ? built-in charge pump for the upper side gate drive voltage generation ? speed discriminator and pll speed control system ? high efficiency drive by synchronous rectification ? 5v regulator output ? start/stop switching circuit(power save state in a stop mode) ? forward/reverse switching circuit ? braking circuit (short braking) ? built-in fg amplifier and integrating amplifier ? built-in vco circuit ? speed lock detection output ? current limiter ? constaint protection circuit ? clock disconnection protection circuit ? thermal shutdown protection circuit ? low-voltage protection circuit specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 31710 sy 20100219-s00001 no.a1677-1/19
LV8104V no.a1677-2/19 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max v cc = vg 42 v charge pump output voltage vg max vg pin 42 v i o max1 pins ul, vl, wl -15 to 15 ma output current i o max2 pins uh, vh, wh, uout, vout and wout -15 to 15 ma pd max1 independent ic 0.65 w allowable power dissipation pd max2 mounted on the specified board * 1.70 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c * specified board:114.3mm 76.1mm 1.6mm, glass epoxy board. allowable operating range at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 16 to 28 v 5v constant voltage output current i reg 0 to -10 ma ld pin applied voltage v ld 0 to 6 v ld pin output current i ld 0 to 5 ma fgs pin applied voltage v fgs 0 to 6 v fgs pin output current i fgs 0 to 5 ma electrical characteristics at ta = 25 c, v cc = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 6.5 8.2 ma supply current 2 i cc 2 at stop 3 3.8 ma 5v constant-voltage output (vreg pin) output voltage vreg i o = 5ma 5.2 5.6 6.0 v line regulation v (reg1) v cc = 16 to 28v 10 50 mv load regulation v (reg2) i o = -5 to -10ma 10 50 mv output block / conditions : apply a vg voltage of 33v high level output voltage 1 v oh 1 pins ul, vl and wl i oh = -2ma vreg-0.48 vreg-0.35 vreg-0.22 v low level output voltage 1 v ol 1 pins ul, vl and wl i ol = 2ma 0.19 0.30 0.41 v high level output voltage 2 v oh 2 pins uh, vh and wh i oh = -2ma vg-0.65 vg-0.5 vg-0.35 v low level output voltage 2 v ol 2 pins uh, vh and wh i ol = 2ma 0.45 0.6 0.8 v pwm frequency f (pwm) 16 20 24 khz internal oscillator oscillation frequency f (ref) 1.79 2.24 2.69 mhz charge pump output (vg pin) output voltage vgout v cc +7.9 v cc +9.0 v cc +10.0 v cp1 pin high level output voltage v oh (cp1) icp1 = -2ma v cc -1.45 v cc -1.1 v cc -0.8 v low level output voltage v ol (cp1) icp1 = 2ma 0.5 0.65 0.8 v charge pump frequency f (cp1) 112 140 168 khz hall amplifier input bias current i b (ha) -2 -0.1 a common-mode input voltage range 1 vicm1 when using hall elements 0.3 3.5 v common-mode input voltage range 2 vicm2 at one-si de input bias (hall ic application) 0 vreg v hall input sensitivity sin wave 50 mvp-p hysteresis width v in (ha) 5 13 24 mv input voltage low high vslh 2 7 12 mv input voltage high low vshl -12 -6 -2 mv continued on next page.
LV8104V no.a1677-3/19 continued from preceding page. ratings parameter symbol conditions min typ max unit fg amplifier input offset voltage v io (fg) -10 10 mv input bias current ib (fg) -1 1 a reference voltage vb (fg) -5% vreg/2 5% v high level output voltage v oh (fg) ifgi = -0.1ma, no load 3.95 4.4 4.85 v low level output voltage v ol (fg) ifgi = 0.1ma, no load 0.75 1.2 1.65 v fg input sensitivity gain : 100 times 3 mv schmitt width of the next stage one-side hysteresis comparator 120 200 280 mv operation frequency range 3 khz open-loop gain f fg = 2khz 45 48 db fgs output output saturation voltage v ol (fgs) i fgs = 2ma 0.2 0.4 v output leakage current il (fgs) v o = 6v 10 a csd oscillator high level output voltage v oh (csd) 2.9 3.4 3.9 v low level output voltage v ol (csd) 1.6 2.0 2.4 v amplitude v (csd) 1.15 1.4 1.65 vp-p external capacitor charge current ichg1 -13 -10 -7 a external capacitor discharge current ichg2 7.5 10.5 13.5 a oscillation frequency f (csd) c = 0.047 f 78 hz speed discriminator output high level output voltage v oh (d) vreg-1.25 vreg-1.0 vreg-0.75 v low level output voltage v ol (d) 0.65 0.9 1.15 v counts 512 ld output output saturation voltage v ol (ld) i ld = 2ma 0.2 0.4 v output leakage current i l (ld) v o = 6v 10 a lock range -6.25 +6.25 % speed control pll output high level output voltage v oh (p) vreg-2.0 vreg-1.7 vreg-1.4 v low level output voltage v ol (p) 1.3 1.6 1.9 v current control circuit drive gain gdf 0.20 0.25 0.32 current limiter operation limiter voltage vrf 0.225 0.25 0.27 v integrator input offset voltage v io (int) -10 10 mv input bias current i b (int) -1 1 a reference voltage v b (int) -5% vreg/2 5% v high level output voltage v oh (int) i int i = -0.1ma, no load 3.95 4.4 4.85 v low level output voltage v ol (int) i int i = 0.1ma, no load 0.75 1.2 1.65 v open-loop gain f int = 2khz 45 48 db vco oscillator (c pin) oscillation frequency range f (c) c = 120pf, r = 24k 0.15 1.54 mhz high level output voltage v oh (c) fil = 2.5v 2.71 3.16 3.61 v low level output voltage v ol (c) fil = 2.5v 2.20 2.60 3.00 v amplitude v (c) fil = 2. 5v 0.44 0.56 0.68 vp-p fil pin output source current i oh (fil) -15 -11 -6 a output sink current i ol (fil) 6 10 15 a continued on next page.
LV8104V no.a1677-4/19 continued from preceding page. ratings parameter symbol conditions min typ max unit low-voltage protection circuit operation voltage vl vsd 10.0 10.7 11.4 v hysteresis width vlvsd 0.72 0.97 1.22 v thermal shutdown operation thermal shutdown operation temperature tsd design target value* 150 175 c hysteresis width tsd design target value* 30 c clk pin input frequency fi (clk) 3 khz high level input voltage range v ih (clk) 2.0 vreg v low level input voltage range v il (clk) 0 1.0 v input open voltage v io (clk) vreg-0.5 vreg v hysteresis width v is (clk) design target value* 0.18 0.27 0.36 v high level input current i ih (clk) vclk = 5v -22 -10 -3 a low level input current i il (clk) vclk = 0v -133 -93 -70 a pull-up resistance ru (clk) 45 60 75 k s/s pin high level input voltage range v ih (s/s) 2.0 vreg v low level input voltage range v il (s/s) 0 1.0 v input open voltage v io (s/s) vreg-0.5 vreg v hysteresis width v is (s/s) 0.18 0.27 0.36 v high level input current i ih (s/s) vs/s = 5v -22 -10 -3 a low level input current i il (s/s) vs/s = 0v -133 -93 -70 a pull-up resistance ru (s/s) 45 60 75 k f/r pin high level input voltage range v ih (f/r) 2.0 vreg v low level input voltage range v il (f/r) 0 1.0 v input open voltage v io (f/r) vreg-0.5 vreg v hysteresis width v is (f/r) 0.18 0.27 0.36 v high level input current i ih (f/r) vf/r = 5v -22 -10 -3 a low level input current i il (f/r) vf/r = 0v -133 -93 -70 a pull-up resistance ru (f/r) 45 60 75 k br pin high level input voltage range v ih (br) 2.0 vreg v low level input voltage range v il (br) 0 1.0 v input open voltage v io (br) vreg-0.5 vreg v hysteresis width v is (br) 0.18 0.27 0.36 v high level input current i ih (br) vbr = 5v -22 -10 -3 a low level input current i il (br) vbr = 0v -133 -93 -70 a pull-up resistance ru (br) 45 60 75 k note : * these items are design target values and are not tested.
LV8104V package dimensions unit : mm (typ) 3277 sanyo : ssop44(275mil) 7.6 15.0 0.65 5.6 (0.68) (1.5) 44 23 1 22 0.22 0.5 0.2 0.1 1.7max pd max - ta 0 1.0 1.7 0.5 0.65 1.5 ? 20 80 0.95 0.36 60 20 40 0 100 independent ic ambient temperature, ta -c allowable power dissipation, pd max -w specified board : 114.3 76.1 1.6mm 3 glass epoxy mounted on a board 2.0 pin assignment 1 37 38 39 40 41 42 43 44 lv8104 vreg 2 gnd2 3 gnd1 4 c 5 r 6 csd 7 intin 8 intref 9 dout 10 s/s 11 f/r 12 fgs 36 wh 35 wout 34 wl 33 vh 32 vout 31 vl 30 uh 29 uout 28 ul 27 26 rf 25 rfgnd nc v cc vg cp2 cp1 nc 24 23 22 21 20 19 18 17 16 15 14 13 in3 + pout clk br ld fgout fgin + fgin - in1 - fil intout in3 - in2 + in2 - in1 + no.a1677-5/19
LV8104V three-phase logic truth table (a high level input is the state where in + > in - .) f/r = ?l? f/r = ?h? drive output in1 in2 in3 in1 in2 in3 upper gate lower gate 1 h l h l h l vh ul 2 h l l l h h wh ul 3 h h l l l h wh vl 4 l h l h l h uh vl 5 l h h h l l uh wl 6 l l h h h l vh wl s/s input br input input mode input mode high or open stop high or open brake low start low release current control characteristics rf ? intout (typical characteristics) 0 0.2 0.25 0.1 0.3 1.5 3.5 2.5 3.0 3.2 2.0 2.2 4.0 intout ? v rf?v gain = 0.25 no.a1677-6/19
LV8104V block diagram (referance constants) + fgs dout fgout r c fil clk fgin - fgin + vreg vreg int out int in int ref 24v v cc hall hys comp hall fil in3 + in3 - in2 + in2 - in1 + dout pout in1 - csd br rf gnd2 gnd1 f/r rfgnd s/s vreg pre driver drive logic + - + - vh vout 680pf 680pf 680pf vl fw217 3 4700pf 4700pf 4700pf 150pf 5% 120pf 680pf 680pf 680pf uh vg cp2 cp1 uout ul wh wout wl vreg + - ld vreg vreg br rst f/r s/s curr comp int osc lvsd charge pump control amp speed discri speed pll vco fg fil latch 1/112 1/16 pout ld 1/512 vco pll csd osc fgs clk no.a1677-7/19
LV8104V relations hall input with drive output (1) when f/r = ?l? in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output (2) when f/r = ?h? in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output no.a1677-8/19
LV8104V (3) when f/r = ?l? and the inverting phase input as against hall input(2). no.a1677-9/19 (4) when f/r=?h? and the inverting ph ase input as against hall input(1). in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output in1 in2 in3 uh vh wh ul vl wl pwm control output synchronous rectification output
LV8104V pin functions pin no. pin name pin function equivalent circuit 1 vreg 5v constant voltage output pin(5.6v). connect a capacitor between this pin and gnd. 1 v cc 2 3 gnd2 gnd1 gnd pins. gnd1 and gnd2 are connected in the ic. 4 c vco oscillation pin. connect a capacitor between this pin and gnd. 4 vreg 5 r pin to set the charge / discharge current of the vco circuit. connect a resistor between this pin and gnd. vreg 5 6 fil vco pll output filter pin. vreg 6 continued on next page. no.a1677-10/19
LV8104V continued from preceding page. pin no. pin name pin function equivalent circuit 7 csd pin to set the operating time of the constraint protection. connect a capacitor between this pin and gnd. this pin combines also functions as the logic circuit block initial reset pin. 7 vreg reset circuit 8 intout integrating amplifier output pin. vreg 8 9 intin integrating amplifier inverting input pin. 10 intref integrating amplifier non-inverting input pin. 1/2 vreg potential. connect a capacitor between this pin and gnd. vreg 9 intout 10 11 dout speed discriminator output pin. acceleration high, deceleration low. vreg 11 12 pout speed control pll output pin. outputs the phase comparison result for clk and fg. vreg 12 continued on next page. no.a1677-11/19
LV8104V continued from preceding page. pin no. pin name pin function equivalent circuit 13 s/s start / stop control pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. low for start. the hysteresis widt h is about 0.27v. 13 vreg 14 clk external clock signal input pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. the hysteresis widt h is about 0.27v. f = 3khz, maximum. 14 vreg 15 f/r forward / reverse control pin. low : 0v to 1.0v high : 2.0v to vreg goes high when left open. low for forward. the hysteresis widt h is about 0.27v. 15 vreg 16 br brake pin(short braking operation). low : 0v to 1.0v high : 2.0v to vreg goes high when left open. high or open for brake mode operation. the hysteresis widt h is about 0.27v. 16 vreg 17 fgs fg amplifier schmitt output pin. this is an open collector output. 17 vreg continued on next page. no.a1677-12/19
LV8104V continued from preceding page. pin no. pin name pin function equivalent circuit 18 ld speed lock detection output pin. this is an open collector output. goes low when the motor speed is within the speed lock range( 6.25%) 18 vreg 19 fgout fg amplifier output pin. this pin is connected to the fg schmitt comparator circuit internally in the ic. 19 vreg fg schmitt comparator 20 fgin - fg amplifier inverting input pin. 21 fgin + fg amplifier non-inverting input pin. 1/2 vreg potential. connect a capacitor between this pin and gnd. vreg 20 fgout 21 22 23 24 25 26 27 in1 - in1 + in2 - in2 + in3 - in3 + hall input pins. the input is seen as a high level input when in + > in - , and as a low level input for the opposite state. if noise on the hall signals is a problem, insert capacitors between the corresponding in + and in - inputs. vreg 23 25 27 26 24 22 28 rfgnd output current detection reference pin. connect to gnd side of the current detection resistor rf. vreg 28 continued on next page. no.a1677-13/19
LV8104V continued from preceding page. pin no. pin name pin function equivalent circuit 29 rf output current detection pin. connect to the current detection resistor rf. sets the the maximum output current iout to be 0.25/rf. vreg 29 30 33 36 ul vl wl output pins for gate drive of the lower side n channel power fet. vreg 30 33 36 32 35 38 uh vh wh output pins for gate drive of the upper side n channel power fet. 31 34 37 uout vout wout pins to detect the source voltage of the upper side n channel power fet. vg 32 35 38 31 34 37 40 v cc power supply pin. connect a capacitor between this pin and gnd for stabilization. 42 vg charge pump output pin. connect a capacitor between this pin and v cc . 43 cp2 pin to connect the capacitor for charge pump. connect a capacitor between this pin and cp1. 42 43 v cc continued on next page. no.a1677-14/19
LV8104V continued from preceding page. pin no. pin name pin function equivalent circuit 44 cp1 pin to connect the capacitor for charge pump. connect a capacitor between this pin and cp2. v cc 44 39 41 nc no connection pins. no.a1677-15/19
LV8104V no.a1677-16/19 description of LV8104V 1. speed control circuit this ic controls the speed with a combination of the speed discriminator circuit and the pll circuit. therefore, when a motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed control method only the speed discriminator. the speed discriminator circuit and the pll circuit outputs an error signal once every one fg period. the fg servo frequency signal (f fg ) is controlled to have the equal frequency with the clock signal (f clk ) which is input through the clk pin. f fg = f clk 2. vco circuit this ic has the vco circuit to generate the reference sign al of the speed discriminator circuit. the reference signal frequency is calculated as follows. f vco = f clk 512 f vco : reference signal frequency, f clk : clock signal frequency the components connected to the r, c and fil pins must be connected to the gnd1 pin (pin 3) with a line that is as short as possible to reduce influence of noise. 3. output drive circuit this ic can be used to implement both upper and lower output n channel power fet drive circuit using a built-in charge pump circuit. the upper side gate voltage is v cc +9v. the lower side gate voltage is vreg(5.6v). the pwm switching is performed on the ul, vl and wl pi ns. therefore, it is performed on the lower output n channel power fet. the driving force of the motor is adju sted by changing the duty that the lower output n channel power fet is on. the pwm frequency is dete rmined with 20khz (typical) in the ic. when the pwm switching of the lower output n channel power fet is off, the upper output n channel power fet is turned on (synchronous rectification). th erefore, it is possible to reduce the te mperature increase of the upper output n channel power fet.the off-time of the synchronous rectification is determined in the ic and varies from 1.7 s to 3.7 s. 4. speed lock range the speed lock range is less than 6.25% of the fixes speed. when the motor sp eed is in the lock range, the ld pin (an open collector output) goes low. if the motor speed goes out of the lock range, the pwm output on-duty is adjusted according to the speed error to control the mo tor speed to be with in the lock range. 5. hall input signal the input amplitude of 100mvp-p or more (differential) is desirable in the hall sensor inputs. the closer the input wave-form is to a square wave, the required input amplitude is lower. inversely, the closer the input waveform is to a triangular wave, the higher input amplitude is required. also, no te that the input dc voltage must be set to be within the common-mode input voltage range. if a hall sensor ic is used to provide the hall inputs, those signals can be input to one side (either the + or - side) of the hall sensor signal inputs as 0 to vreg level signals if the other side is held fixed at a voltage within the common-mode input voltage range that applies when the hall sensors are used. if noise on the hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. those capacitors must be located as close as possible to the input pins. when the hall inputs for all three phases are in the same state, all the outputs will be in the off state. 6. current limiter circuit the current limiter circuit limits the (peak) current at the value i = v rf /rf (v rf = 0.25v (typical), rf : current detection resistor). the current limitation operation consists of reducing the pwm output on-duty to suppress the current. high accuracy detection can be achieved by connecting the rf and rfgnd pins lines near at the ends of the current detection resistor (rf). 7. s/s switching circuit when the s/s pin is set to the low level, s/s switching circuit is the start mode. inversely, when the s/s pin is set to the high level or open, s/s switching circuit is the stop mode. this ic will be in the power save state of decreasing the supply current at the stop mode. the bias cu rrent to most of the circuit in the ic is cut off in the power save state. the operating circuit in the power save stat e are limited to the s/s switching circu it , the 5v constant voltage output, fg amplifier and fg amplifier schmitt output. the other circuit do not operate. the upper side output transistors for all phases (the uh, vh and wh side) and the lower side output transistors for all phases (the ul, vl and wl side) are turned off in the power save state.
LV8104V no.a1677-17/19 8. braking circuit when the br pin is set to the high level or open, the brake is on. inversely, when the br pin is set to the low level, the brake is released. the brake becomes a s hort brake that turns on the upper side output transistors for all phases (the uh, vh and wh side) and turns off the lower side output transistors for all phases (the ul, vl and wl side). note that the current limiter does not operate during br aking. the current that flows in the output transistors during braking is determined by the motor back emf voltage and the coil resistance. applications must be designed so that this current does not exceed the ratings of the output transistors used. (the higher the motor speed at which braking is applied, the more severe this problem becomes). the br pin can be switching at the start mode. (this ic is designed to avoid through currents at changeover.) this means that motor startup and stop control can be performed using the br pin with the s/s pin held at the low level (the start mode). if the startup time becomes excessive, it can be reduced by controlling the motor startup and stop with the br pin rather than with the s/s pin (since the ic will be in the power save state at the stop mode, enough time for the vco circuit to stabilize will be required at the beginning of the motor start operation). 9. forward/reverse switching circuit the motor rotation direction can be switched by using the f/r pin. however, the following notes must be observed if the f/r pin is switched while the motor is rotating. ? this ic is designed to avoid through currents at changeover. however, the rise in the motor supply voltage (due to instantaneous return of the motor current to the power supply) during direction switching may cause problems. if this rise is a problem, the value of the capacitor inse rted between power and ground must be increased. ? if the motor current after direction switching exceeds the current limit value, the pwm drive side outputs will be turned off, but the opposite side output will be in the shor t-circuit braking state, and a current determined by the motor back emf voltage and the coil resistance will flow. applications must be designed so that this current does not exceed the ratings of the output transistors used. (the higher the motor speed at which the direction is switched, the more severe this problem becomes.) 10. constraint protection circuit this ic includes the constraint protection circuit to protect the motor and the output transistors in the motor constrained state. if the ld output remains high (indicating the unlocked state) for a fixed period in the motor drive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. this time can be set by adjusting the oscillation frequency of the csd pin by using a external capacitor. by the value (c) of the capacitor attached to the csd pin, the set time is calculated as follows. the set time (sec) = 60.8 c ( f) when a 0.047 f capacitor is connected with the csd pi n, the set time beco mes about 2.9sec. by the variance of the ic, ?60.8? of the above formula has varied from 40.8 to 80.8. to restart a motor by cancelling the constraint protecti on function, any of the following operation is necessary. ? put the s/s pin into the start state again after the stop mode (about 1ms or more). ? put the br pin into the brake release state agai n after the braking state (about 1ms or more). ? turn on the power supply agai n after the turn off state. when the clock disconnect protection function, the thermal shutdown function and the low-voltage protection function are operating, the constraint protec tion function does not operate even if the motor does not rotate. the oscillation waveform of the csd pin is used as the reference signal for some circuits in addition to the motor constraint protection circuit. therefore, it is desirable to oscillate the csd pin even if the constraint protection function is unnecessary. if the constraint protection circuit is not used, the oscillati on of the csd pin mu st be stopped by connecting a 220k resistor and a 0.01 f capacitor in parallel between the csd pin and gnd. however, in that case, the clock disconnection protection circuit does not operate too. and, the synchronous rectification does not operate in any of the following cases. ? when the motor does not rotate in the motor constrained state since the motor is started up by the s/s or the br input, the pwm switching is performed by using the current limiter circuit. but, the synchronous rectification does not operate when the oscillation of the csd pin is stopped. the csd pin combines also functions as the initial reset pin. the time that the csd pin voltage is charged to about 1.25v is determined as the initial reset. at the initial reset, all the outputs will be in the off state.
LV8104V no.a1677-18/19 11. clock disconnection protection circuit if the clock input through the clk pin goes to the no input state in the motor drive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. if the clock is resupplied, the clock disconnection protection function is cancelled. when the clock period is longer than about thirty-fourth part of the constraint protection set time, the clock disconnection protection circuit judges the clock input to be the no input state and this protection function will operate. 12. thermal shutdown circuit if the junction temperature rises to the sp ecified temperature (tsd) in the motor dr ive state (the s/s pin : start, the br pin : brake release), the lower side output transistors (the ul, vl and wl side) are turned off. if the junction temperature falls to more than the hysteresis width ( tsd), the thermal shutdown function is cancelled. 13. low-voltage protection circuit the ic includes a low-voltage protection circuit to protect against incorrect operation when the v cc power is applied or if the power supply voltage falls below its operating level. when the v cc voltage falls under the specified voltage (vlvsd), all the outputs will be in the off state. if the v cc voltage rises to more than the hysteresis width ( vlvsd), the low-voltage protection function is cancelled. 14. power supply stabilization since this ic is used in applications that flow the large output current, the power supply line is subject to fluctuations. therefore, capacitors with ca pacitance adequate to stabilize the power su pply voltage must be connected between the v cc pin and gnd. if diodes are inserted in the power supply line to prevent the ic destruction due to reverse power supply connection, since this makes the power supply voltage even more subject to fluctuations, even larger capacitance will be required. 15. ground lines the signal system gnd and the output system gnd must be se parated, and connected to one gnd at the connector. as the large current flows to the output system gnd, th is gnd line must be made as short as possible. output system gnd : gnd for rf and v cc line capacitors signal system gnd : gnd for the ic and external components 16. integrating amplifier the integrating amplifier integrates the speed error pulses and phase error pulses and converts them to the speed command voltage. at that time it also sets the control loop gain and the frequency characteristics. external components of the integrating amplifier must be placed as close to the ic as possible to reduce influence of noise. 17. fg amplifier the fg amplifier normally makes up a filter amplifier to rej ect noise. since a clamp circuit has been added at the fg amplifier output, the output amplitude is clamped at abou t 3.2vp-p, even if the amplifier gain is increased. after the fg amplifier, the schmitt comparator on one si de hysteresis(200mv (typical)) is inserted. the schmitt comparator output (fgs output) becomes high level when the fg amplifier output is lower than the fgin + voltage, and becomes low level when the fg amplifier output is higher to more than schmitt width as compared with the fgin + voltage. therefore, it is desirable that the amplifier gain be se t so that the output amplitude is over 1.0vp-p at the lowest controlled speed to be used. the capacitor connect ed between the fgin + pin and gnd is required for bias voltage stabilization. this capacitor must be connected to the gnd1 pin (pin 3) with a line th at is as short as possible to reduce influence of noise. as the fg amplifier and the fgs output ar e operating even if the s/s pin is the stop state, it is possible to monitor the motor rotation by the fgs output.
LV8104V sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2010. specifications and information herein are subject to change without notice. ps no.a1677-19/19

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